The present invention relates to level shifter circuits, and in particular to level shifter circuits having increased switching speed.
The feature size of transistors in CMOS technology continues to shrink as technology advances. As a result, the core supply voltage of integrated circuits also drops. For example, when feature sizes shrink from 0.15 nm technology to 90 nm technology the core supply voltage drops to 0.9V from 1.5V. However, when interfacing the integrated circuit with external components, in many cases it needs to be compatible with older technologies having a 3.3V supply. Therefore, a level shifter circuit is required to convert the signals in from the core supply level to the IO supply level in order to communicate with outside components.
The class of integrated circuits that includes user-programmable integrated circuits such as field programmable gate array (FPGA) integrated circuits generally includes two types of transistors. Transistors having 50 Angstrom thick gate oxide layers are slow due to their relatively thick gate oxide layers, but can sustain 3.6V. These devices are used to build logic circuits to work with 1.8V, 2.5V, and 3.6V power supplies. Transistors having 20-Angstrom thick gate oxide layers are fast due to their relatively thin gate oxide layers, but can sustain only 1V power supplies. These devices are used to build logic circuits in the core of FPGA.
FPGA integrated circuits usually employ general-purpose input/output (GPIO) circuits targeted for high voltage standards like LVCMOS33/25 PCI. The maximum voltage is 3.6 v. The 2.5V device can withstand 3.6 v by increasing its length proportionately. A conventional level shifter circuit can fulfill the task of converting a 1.5V signal to a 3.3V signal. However, in 90 nm technology or other technologies that provide a very low core supply voltage, present level shifter circuits can only handle relatively low speed signals.
This problem in the prior art is most acute when the integrated circuit must drive an external component such as DDR3/4 memory. For example, DDR3 memory has a minimum speed requirement of 300 MHz.
Previous generation GPIO circuits do not have DDR3 capability. A current challenge in GPIO circuits is the internal block design (level shifter/pre-driver) is to be able to use extra length 2.5 v thick oxide transistors for reliability and still make DDR3 speeds.
Current GPIO circuits are speed restricted due to usage of these extra-long thick oxide devices (need to tolerate up to 3.6 v) in its logic. Advanced techniques are needed to improve the speed and performance at DDR3/4 speeds.
Therefore, there is a need for a new method for a level shifter circuit that overcomes the disadvantages of the prior art and fulfills the need to provide drive for external DDR circuits.